p p js6 60 2 september 18,2015 - rev.00 page 1 2 0 v complementary enhancement mode mosfet voltage 20 / - 2 0v current 5.2 / - 3 .4 a sot - 23 6l unit: inch(mm) f eatures ? advanced trench process technology ? specially designed for switch load, pwm application, etc. ? lead free in compliance with eu rohs 2011/65/eu directive ? green molding compound as per iec61249 std. (halogen free) mechanical data ? case: sot - 23 6l package ? terminals : solderable per mil - std - 750, method 2026 ? approx. weight: 0.0005 ounces, 0.014 grams ? m arking: sc 2 parameter symbol n - ch limit p - ch limit units drain - source voltage v ds 2 0 - 2 0 v gate - source voltage v gs + 12 + 12 v continuous drain current i d 5.2 - 3 . 4 a pulsed drain current (note 4 ) i dm 20.8 - 1 3.6 a power dissipation t a =25 o c p d 1.2 5 w derate above 25 o c 10 m w/ o c operatin g junction an d storage temperature range t j ,t stg - 55~150 o c typical thermal r esistance - j unction to ambient (note 3 ) r ja 100 o c /w maximum ratings and thermal characteristics (t a =25 o c unless otherwise noted)
p p js6 60 2 september 18,2015 - rev.00 page 2 n - channel e lectrical c haracteristics (t a =25 o c unless otherwise noted) notes : 1. pulse width < 300us, duty cycle < 2% 2. essentially independent of operating temperature typical characteristics . 3. r ? ja is the sum of the junction - to - case and case - to - ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins m ounted on a 1 inch fr - 4 with 2oz . square pad of copper . 4. the maximum current rating is package limited. 5. guaranteed by design, not subject to product ion testing parameter symbol test condition min. typ. max. units static drain - source break down voltage bv dss v gs = 0 v, i d = 25 0ua 2 0 - - v gate threshold voltage v gs(th) v ds =v gs , i d = 250 ua 0.5 0.77 1.2 v drain - source on - state resistance r ds(on) v gs = 4.5 v, i d = 5.2 a - 29 36 m gs = 2.5 v, i d = 3.2 a - 39 52 v gs = 1.8 v, i d = 1.5 a - 58 92 zero gate volt age drain current i dss v ds = 20 v, v gs =0v - - 1 u a gate - source leakage current i gss v gs = + 12 v, v ds =0v - - + 10 0 n a dynamic (note 5 ) total gate charge q g v ds = 10 v, i d = 5.2 a, v gs = 4.5v (note 1 , 2 ) - 4.1 - nc gate - source charge q gs - 1.1 - gate - drain charge q gd - 0.7 - input capacitance ciss v ds = 10 v, v gs = 0 v, f=1.0mhz - 396 - pf output capacitance coss - 54 - reverse transfer capacitance crss - 40 - turn - on delay time t d (on) v dd = 10 v, i d = 5.2 a, v g s = 4.5v, r g = 6 (note 1 , 2 ) - 14 - ns turn - on rise time tr - 10 - turn - o ff delay time t d (off) - 30 - turn - o ff fall time tf - 7 - drain - source diode maximum continuous drain - source diode forward current i s --- - - 1.5 a diode forward voltage v sd i s = 1.0 a, v gs = 0 v - 0.75 1.2 v
p p js6 60 2 september 18,2015 - rev.00 page 3 p - channel electrical characteristics (t a =25 o c unless otherwise noted) parameter symbol test condition min. typ. max. units static drain - source breakdown voltage bv dss v gs = 0 v, i d = - 25 0ua - 2 0 - - v gate threshold voltage v gs(th) v ds =v gs , i d = - 250 ua - 0.4 - 0.65 - 1.2 v drain - source on - state resi stance r ds(on) v gs = - 4.5 v, i d = - 3.4 a - 65 82 m gs = - 2.5 v, i d = - 2.2 a - 82 110 v gs = - 1.8 v, i d = - 1.2 a - 103 146 zero gate voltage drain current i dss v ds = - 20 v, v gs =0v - - - 1 u a gate - source leakage current i gss v gs = + 12 v, v ds =0v - - + 10 0 n a dynamic (note 5 ) total gate charge q g v ds = - 10 v, i d = - 3.4 a, v gs = - 4.5v (note 1 , 2 ) - 7 - nc gate - source charge q gs - 1 - gate - drain charge q gd - 1.8 - input capacitance ciss v ds = - 10 v, v gs = 0 v, f=1.0mhz - 522 - pf output capacitance coss - 55 - reverse transfer ca pacitance crss - 40 - turn - on delay time t d (on) v dd = - 10 v, i d = - 3.4 a, v g s = - 4.5v, r g = 6 (note 1 , 2 ) - 10 - ns turn - on rise time tr - 4 - turn - o ff delay time t d (off) - 34 - turn - o ff fall time tf - 5 - drain - source diode maximum continuous drain - source diode forward current i s --- - - - 1.5 a diode forward voltage v sd i s = - 1.0 a, v gs = 0 v - 0.77 - 1.2 v notes : 1. pulse width < 300us, duty cycle < 2% 2. essentially independent of operating temperature typical characteristics . 3. r ? ja is the sum of the junction - to - case and case - to - ambient thermal resistance where the case thermal reference is defin ed as the solder mounting surface of the drain pins m ounted on a 1 inch fr - 4 with 2oz . square pad of copper . 4. the maximum current rating is package limited. 5. guaranteed by design, not subject to product ion testing.
p p js6 60 2 september 18,2015 - rev.00 page 4 n - channel t ypical characteristic cur ves fig.1 on - region characteristics fig. 2 transfer characteristics fig. 3 on - resistance vs. drain current fig. 4 on - resistance vs. junction temperature fig. 5 on - resistance variation with vgs. fig. 6 body dlode characterlslcs
p p js6 60 2 september 18,2015 - rev.00 page 5 n - channel t ypical characteristic curves fig. 7 gate - charge characteristics fig. 8 threshold voltage variation with temperature . fig. 9 capacitance vs. drain - source voltage.
p p js6 60 2 september 18,2015 - rev.00 page 6 p - channel t ypical characteristic curves fig.1 on - region characteristics fig. 2 transfer characteristics fig. 3 on - resistance vs. drain current fig. 4 on - resistance vs. junction temperature fig. 5 on - resistance variation with vgs. fig. 6 body dlode characterlslcs
p p js6 60 2 september 18,2015 - rev.00 page 7 p - channel t ypical characteristic curves fig. 7 gate - charge characteristics fig. 8 threshold voltage variation with temperature . fig. 9 threshold voltage variation with temperature .
p p js6 60 2 september 18,2015 - rev.00 page 8 part no p acking code version mounting pad layout part no packing code package type packing type marking ver sion PJS6602 _ s 1_00001 sot - 23 6l 3k pcs / 7
p p js6 60 2 september 18,2015 - rev.00 page 9 disclaimer
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